Integrated circuits are made up of millions of active devices formed in or on a substrate, such as a silicon wafer. In one manufacturing process, a dielectric substrate is patterned by a conventional dry etch process to form holes and trenches for vertical and horizontal interconnects. The patterned surface is then optionally coated with a diffusion barrier layer and/or an adhesion-promoting layer, followed by deposition of a metal layer to fill the trenches and holes. Chemical-mechanical polishing (CMP) is employed to reduce the thickness of the metal layer, as well as the thickness of the diffusion barrier layer and/or adhesion-promoting layer, until the underlying dielectric layer is exposed, thereby forming the circuit device.
One way to fabricate planar metal circuit traces on a silicon dioxide substrate is referred to as the damascene process. In accordance with this process, the silicon dioxide dielectric surface having optionally a layer of silicon nitride deposited thereon is patterned by applying a photoresist, exposing the photoresist to irradiation through a pattern to define trenches and/or vias, and then using a conventional dry etch process to form holes and trenches for vertical and horizontal interconnects. The silicon nitride functions as a “hard mask” to protect the silicon dioxide surface that is not part of the trenches and/or vias from damage during etching. The patterned surface is coated with an adhesion-promoting layer such as titanium or tantalum and/or a diffusion barrier layer such as titanium nitride or tantalum nitride. The adhesion-promoting layer and/or the diffusion barrier layer are then over-coated with a metal layer. Chemical-mechanical polishing is employed to reduce the thickness of the metal over-layer, as well as the thickness of any adhesion-promoting layer and/or diffusion barrier layer, until a planar surface that exposes elevated portions of the silicon oxide surface is obtained. The vias and trenches remain filled with electrically conductive metal forming the circuit interconnects.
Tungsten and copper are most frequently used as the electrically conductive metal. However, aluminum, which had been used in earlier generation processes to fabricate circuit interconnects via subtractive processes such as etching techniques, has been under increasing consideration for use in damascene processes. The combination of aluminum and titanium offers potentially lower resistivity than other metal/barrier layer combinations, with corresponding potential improvement in circuit performance.
Polishing compositions for aluminum damascene structures comprising alumina abrasives treated with sulfonate-containing polymers or copolymers have been described. While the sulfonate-containing polymers or copolymers are intended to confer colloidal stability to the alumina abrasives, the presence of other polishing components such as complexing agents, topography control agents, and surface treatment polymers can result in displacement of the sulfonate-containing polymers or copolymers from the alumina abrasive particles, with the result that colloidal stability of the polishing compositions is compromised. Interparticle agglomeration leading to large particles can lead to scratching and other surface defects on substrates being polished. Thus, there remains a need in the art for improved methods of polishing aluminum-containing substrates.